1. Field of the Invention
This invention relates to a semiconductor circuit device called a Schottky junction Field-Effect Transistor, or a Schottky gate FET, or a MEtal-Semiconductor Field-Effect Transistor (MESFET), and a method for production thereof.
2. Description of the Prior Art
As is well known, the semiconductor circuit device is a transistor having a basic structure as illustrated in FIG. 1. A relatively high resistant n type semiconductor layer 2 serving as a channel is formed on a semi-insulating substrate 1. Onto the n type semiconductor layer 2 are joined a metal gate 3 making a Schottky contact with a channel 2c, and a source 4 and a drain 5 making an ohmic contact with the channel 2c with the gate 3 being interposed therebetween.
The operating principle for the semiconductor circuit device is that a depletion region 6 occurs at the junction between the gate 3 and the channel 2c owing to a reverse voltage applied to the gate 3, thereby narrowing the width of the channel 2c, the path for electrons. In this device, therefore, the channel width is varied by a gate voltage to control a drain current.
So far, three methods have been known for producing such a semiconductor circuit device.
A first method will be explained hereinbelow with reference to the formation of two transistors on one substrate. This method is composed of the following 5 steps as shown in FIGS. 2A through 2E:
A) A semi-insulating semiconductor substrate 1 comprising a III-V compound semiconductor is made ready for use. A GaAs substrate is used, for example. PA0 B) A patterned mask layer 10A is formed on the substrate 1. With the mask layer 10A used as a mask, n type impurity ions 11A are implanted to form an ion implanted region 2A. PA0 C) After the mask layer 10A is removed, a patterned mask layer 10B is formed on the substrate 1. With the mask layer 10B used as a mask, n type impurity ions 11B are implanted to form an ion implanted region 2B. PA0 D) After the mask layer 10B is removed, the substrate is annealed to activate the implanted ions and convert the ion implanted regions 2A, 2B into active layers (n type semiconductor regions). On the ion implanted regions 2A, 2B are formed metal gates 3 which make a Schottky contact with these regions. PA0 E) On the ion implanted regions 2A, 2B and on both sides of the gate 3 are formed a source electrode 4 and a drain electrode 5 which make an ohmic contact with these regions. PA0 A) A semi-insulating semiconductor substrate 1 comprising a III-V compound semiconductor is made ready for use. A GaAs substrate is used, for example. A conductive semiconductor layer 2 is grown on the substrate 1. PA0 B) A patterned mask layer 10A is formed on the conductive semiconductor layer 2. With the mask layer 10A used as a mask, the conductive semiconductor layer 2 is etched to a desired thickness. C) With the mask 10A being retained, a patterned mask layer 10B is formed on the remaining surface of the conductive semiconductor layer 2. With the mask layers 10A, 10B used as masks, those portions of the conductive semiconductor layer 2 which are other than the portions covered by these mask layers 10A, 10B are removed by etching. PA0 D) After the mask layers 10A, 10B are removed, metal gates 3 which make a Schottky contact with the conductive semiconductor layers 2, 2 are formed on these layers. PA0 E) On each conductive semiconductor layer 2 and on both sides of the gate 3 are formed a source electrode 4 and a drain electrode 5 which make an ohmic contact with the layer 2. PA0 A) A semi-insulating semiconductor substrate 1 comprising a III-V compound semiconductor is made ready for use. A GaAs substrate is used, for example. PA0 B) A patterned mask layer 10A is formed on the substrate 1. With the mask layer 10A used as a mask, n type impurity ions 11A are implanted to form an ion implanted region 2A. PA0 C) With the mask 10A being retained, a patterned mask layer 10B is formed on the remaining surface of the substrate 1, i.e. of the ion implanted region 2A. With the mask layer 10B used as a mask, n type impurity ions 11B are implanted on both sides of the ion implanted region 2A to form ion implanted regions 2B, 2B. PA0 D) After the mask layers 10A, 10B are removed, the substrate is annealed to activate the implanted ions and convert the ion implanted regions 2A, 2B into active layers. On the ion implanted region 2A is formed a metal gate 3 which makes a Schottky contact with this region. PA0 E) On the ion implanted region 2B and on both sides of the gate 3 are formed a source electrode 4 and a drain electrode 5 which make an ohmic contact with this region. PA0 a semi-insulating semiconductor substrate comprising a first III-V compound semiconductor, PA0 a semi-insulating barrier layer comprising InGaP with a wider energy bandgap than that of the first III-V compound semiconductor, and being formed on the semi-insulating semiconductor substrate, PA0 an n type semiconductor region being formed in an upper portion of the semiconductor substrate in contact with the barrier layer, and having n type impurity ions diffused in the semiconductor substrate as a matrix, PA0 a semi-insulating cap layer comprising a semiconductor with a narrower energy bandgap than that of the InGaP and free from In as a constituent element, and being formed on the barrier layer, PA0 a refractory metal gate electrode being formed on the cap layer above the n type semiconductor region, and making a Schottky junction with the cap layer, and PA0 a source electrode and a drain electrode being formed at opposite positions across the gate electrode on the cap layer above the n type semiconductor region, and being connected in an ohmic manner to the n type semiconductor region through the cap layer and the barrier layer. PA0 a step of forming on a semi-insulating semiconductor substrate comprising a first III-V compound semiconductor a semi-insulating barrier layer comprising InGaP with a wider energy bandgap than that of the first III-V compound semiconductor, PA0 a step of forming a semi-insulating cap layer comprising a semiconductor with a narrower energy bandgap than that of the InGaP and free from In as a constituent element, PA0 a step of forming a patterned mask layer on the cap layer, and implanting n type impurity ions into the substrate through the mask layer as a mask to form an n type impurity ion implanted region, PA0 a step of depositing an annealing cap film on the cap layer after the mask layer is removed, and annealing the substrate to activate the impurity ion implanted region and convert it into an n type semiconductor region, PA0 a step of providing an opening at a position of the annealing cap film above the n type semiconductor region, and forming a gate electrode comprising a refractory metal, and PA0 a step of providing openings at opposite positions, across the gate electrode, of the annealing cap film, and forming a source electrode and a drain electrode. PA0 a step of forming a first patterned mask layer on a semi-insulating semiconductor substrate comprising a first III-V compound semiconductor, and implanting n type impurity ions into the substrate through the first mask layer as a mask to form a first n type impurity ion implanted region, PA0 a step of forming second mask layer with a pattern different from that of the first mask layer on the semi-insulating semiconductor substrate after the first mask layer is removed, and implanting n type impurity ions through the second mask layer as a mask to form a second impurity ion implanted region, PA0 a step of forming a semi-insulating barrier layer comprising InGaP with a wider energy bandgap than that of the first III-V compound semiconductor on the substrate after the second mask layer is removed, PA0 a step of forming a semi-insulating cap layer comprising a semiconductor with a narrower energy bandgap than that of the InGaP and free from In as a constituent element, PA0 a step of depositing an annealing cap film on the cap layer, and annealing the substrate to activate the impurity ion implanted region and convert it into an n type semiconductor region, PA0 a step of providing an opening at a position of the annealing cap film above the n type semiconductor region, and forming a gate electrode comprising a refractory metal, and PA0 a step of providing openings at opposite positions, across the gate electrode, of the annealing cap film, and forming a source electrode and a drain electrode. PA0 a step of forming on a semi-insulating semiconductor substrate comprising a first III-V compound semiconductor a semi-insulating barrier layer comprising InGaP With a wider energy bandgap than that of the first III-V compound semiconductor, PA0 a step of forming a semi-insulating cap layer comprising a semiconductor with a narrower energy bandgap than that of the InGaP and free from In as a constituent element, PA0 a step of forming a first mask layer with a desired pattern on the cap layer, and implanting n type impurity ions from the cap layer side through the first mask layer as a mask to form a first impurity ion implanted region, PA0 a step of forming a gate electrode comprising a refractory metal on the cap layer above the ion implanted region after the mask layer is removed, PA0 a step of forming a second mask layer with a pattern different from that of the first mask layer on the cap layer, and implanting n type impurity ions from the cap layer side through the second mask layer and the gate electrode as masks to form a second impurity ion implanted region, PA0 a step of depositing an annealing cap film on the cap layer after the second mask layer is removed, and annealing the substrate to activate the impurity ion implanted region and convert it into an n type semiconductor region, and PA0 a step of providing openings at opposite positions, across the gate electrode, of the annealing cap film, and forming a source electrode and a drain electrode. PA0 a step of forming a first patterned mask layer on a semi-insulating semiconductor substrate comprising a first III-V compound semiconductor, and implanting n-type impurity ions into the substrate through the first mask layer as a mask to form a first n type impurity ion implanted region, PA0 a step of forming a semi-insulating barrier layer comprising InGaP with a wider energy bandgap than that of the first III-V compound semiconductor on the substrate after the first mask layer is removed, PA0 a step of forming a semi-insulating cap layer comprising a semiconductor with a narrow energy bandgap than that of the InGaP and free from In as a constituent element, PA0 a step of forming a gate electrode comprising a refractory metal on the cap layer above the ion implanted region, PA0 a step of forming a second mask layer with a pattern different from that of the first mask layer on the cap layer, and implanting n type impurity ions from the cap layer side through the second mask layer and the gate electrode as masks to form a second impurity ion implanted region, PA0 a step of depositing an annealing cap film on the cap layer after the second mask layer is removed, and annealing the substrate to activate the impurity ion implanted region and convert it into an n type semiconductor region, and PA0 a step of providing openings at opposite positions, across the gate electrode, of the annealing cap film, and forming a source electrode and a drain electrode.
A second method will be explained hereinbelow with reference to the formation of two transistors on one substrate. This method is composed of the following 5 steps as shown in FIGS. 3A through 3E:
A third method will be explained hereinbelow with reference to the formation of one transistor on one substrate. This method is composed of the following 5 steps as shown in FIGS. 4A through 4E:
The above-described first method and second method are both capable of producing two transistors with different characteristics on a single substrate. Compared with the second method involving etching done twice, the first method using the ion implantation technique is evidently easier to carry out.
The third method, on the other hand, is advantageous in that the n type semiconductor region connected to the source electrode and the n type semiconductor region connected to the drain electrode can have a sufficiently high n type impurity concentration, and source electrode resistance and drain electrode resistance can be lowered. Such a semiconductor circuit device of a structure with a low source electrode resistance and a low drain electrode resistance can be prepared by a method employing etching, like the second method. Clearly, however, the third method is easier to perform than the method using etching.
Of the conventional, methods, the first and third methods are thus superior to the other method. However, the two methods and semiconductor circuit devices obtained by them pose the following problems:
In semiconductor circuit devices obtained by the first and third methods, the n type semiconductor region serving as the active layer is formed by implanting ions into the semi-insulating semiconductor substrate. Therefore, the characteristics of the active layer formed depend on the material characteristics of the semi-insulating semiconductor substrate, the matrix. The semi-insulating semiconductor substrate material often contains impurities, undesirable for the characteristics of the active layer, in amounts that cannot be neglected. Consequently, these conventional methods involve the first problem that the semiconductor circuit device produced cannot exhibit the intended characteristics.
Furthermore, the n type semiconductor region serving as the active layer is formed by implanting ions into the semi-insulating semiconductor substrate, as has been stated previously. Thus, the semi-insulating semiconductor substrate portion and the active layer are integral and have no interface therebetween. That is, the surface of the n type semiconductor region that functions as the active layer and the surface of the semi-insulating semiconductor substrate are coplanar. This means that there is no layer which will prevent electrons in the n type semiconductor region from migrating onto the surface of the semi-insulating semiconductor substrate. On the surface of the semi-insulating semiconductor substrate, on the other hand, a defect layer is often formed during or after the production of the device. In the presence of this defect layer on the surface of the semi-insulating semiconductor substrate, electrons in the n type semiconductor region easily arrive at the defect layer, because there is no layer which will prevent such electrons from migrating onto the surface of the semi-insulating semiconductor substrate, as has been described. As a result, when the transistor becomes operative, noises occur in the defect layer, deteriorating the performance of the device noticeably. This is a second problem with the aforementioned conventional methods, and semiconductor devices produced by them.
No solutions have been proposed to the first problem, while the following solution has been put forward to the second problem:
The solution is in the method described in the three publications: Japanese Patent Application Laying-open No. 216636/1992 (Japanese Patent Application No. 411177/1990), "GaAs SURFACE PASSIVATION BY InGaP THIN FILM," Mat. Res. Soc. Symp. Proc. Vol. 240, pb. 777-781, and "Si-implanted InGaP/GaAs metal-semiconductor field-effect transistors," Appl. Phys. Lett. 60(16), 20 Apr. 1992. The method described in these publications comprises forming on a substrate comprising GaAs an InGaP layer having a wider energy bandgap than that of the substrate, and implanting impurity ions into the GaAs substrate through the InGaP layer to form an impurity ion implanted region which will function as an active layer. This method is free from the above-described drawback that electrons in the impurity ion implanted region serving as the active layer move and reach the defect layer present on the substrate surface, since the InGaP barrier layer with a wide energy bandgap is interposed between the substrate surface and the impurity ion implanted region.
An attempt to attain further improvements in efficiency and performance in that method and the semiconductor circuit device obtained thereby, however, causes anew the problems described below.
A method for producing a semiconductor circuit device efficiently using a refractory metal as a gate electrode material has been proposed which comprises implanting impurity ions into the substrate through the gate electrode as a mask, annealing the substrate as such to activate the impurity ion implanted region. This method is introduced, say, in "Reactively sputtered WSiN film suppresses As and Ga outdiffusion," J. Vac. Sci. Technol. B 6(5), September/October 1988, pp. 1526-1529. This literature also reports that WSiN is ideal as a refractory metal for a gate electrode.
When such a method involving the use of a refractory metal as a gate electrode material and the implantation of impurity ions through the gate electrode as a mask is applied to the production of the aforementioned semiconductor circuit device having an InGaP barrier layer, the following problem appears, making the method impracticable.
That is, annealing causes a reaction between the gate electrode and the InGaP layer, deteriorating the Schottky junction characteristics, thus bringing about an ohmic junction. This problem occurs likewise in the presence of heat subsequently applied to the device, even if a gate electrode is formed after the implantation of impurity ions into the substrate is completed and the impurity ion implanted region is activated by annealing.
This invention aims to solve both of the above-mentioned problems: The first of them is that when there is formed an InGaP layer suitable as a barrier layer for preventing the migration of electrons from the impurity implanted region serving as the active layer into the defect layer present on the substrate surface, the Schottky junction deteriorates and becomes an ohmic junction, if the gate electrode making a Schottky contact with the InGaP layer undergoes heat. The second problem is that the active layer is influenced by the material characteristics of the substrate, thus failing to give the desired characteristics. Through this solution, the invention is intended to provide a semiconductor circuit device with high performance.